Integrated circuits are formed from semiconductor substrates within and upon whose surfaces may be formed resistors, transistors, diodes and other electrical circuit elements. As described by Moore's law, the semiconductor industry drives down pattern dimensions in order to reduce transistor size and enhance processor speed at a rapid pace.
As devices scale smaller, shrinking design and demand for doping in the source/drain in p-type MOSFET's lead to increased overlap capacitance. Since high overlap capacitance compromises device alternating current (AC) performance, the scaling of semiconductor devices and components, such as MOSFET's, presents a challenge to fabricating high-quality nano/micron-scale components with good electrical performance.
Thus, a need exists for improved pMOSFET's, for methods of forming the same, and for semiconductor devices incorporating the same.
While certain aspects of conventional technologies have been discussed to facilitate disclosure of the invention, Applicants in no way disclaim these technical aspects, and it is contemplated that the claimed invention may encompass one or more of the conventional technical aspects discussed herein.
In this specification, where a document, act or item of knowledge is referred to or discussed, this reference or discussion is not an admission that the document, act or item of knowledge or any combination thereof was, at the priority date, publicly available, known to the public, part of common general knowledge, or otherwise constitutes prior art under the applicable statutory provisions; or is known to be relevant to an attempt to solve any problem with which this specification is concerned.